HD64F3039F18 Datasheet, PDF (335/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 9 Programmable Timing Pattern Controller
Example of Normal TPC Output (Example of Five-Phase Pulse Output)
Figure 9.5 shows an example in which the TPC is used for cyclic five-phase pulse output.
TCNT value
GRA
TCNT
Compare match
H'0000
NDRA 80
Time
C0 40 60 20 30 10 18 08 88 80 C0 40
PADR 00 80 C0 40 60 20 30 10 18 08 88 80 C0
TP₇
TP₆
TP₅
TP₄
TP₃
• The ITU channel to be used as the output trigger channel is set up so that GRA is an output compare
register and the counter will be cleared by compare match A. The trigger period is set in GRA.
The IMIEA bit is set to 1 in TIER to enable the compare match A interrupt.
• H'F8 is written in PADDR and NDERA, and bits G1CMS1, G1CMS0, G0CMS1, and G0CMS0 are set in
TPCR to select compare match in the ITU channel set up in step 1 as the output trigger.
Output data H'80 is written in NDRA.
• The timer counter in this ITU channel is started. When compare match A occurs, the NDRA contents
are transferred to PADR and output. The compare match/input capture A (IMFA) interrupt service routine
writes the next output data (H'C0) in NDRA.
• Five-phase overlapping pulse output (one or two phases active at a time) can be obtained by writing
H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88... at successive IMFA interrupts.
Figure 9.5 Normal TPC Output Example (Five-Phase Pulse Output)
Rev.3.00 Mar. 26, 2007 Page 311 of 682
REJ09B0353-0300