HD64F3039F18 Datasheet, PDF (133/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 5 Interrupt Controller
2. Generation Conditions
(1) A read of the ISR register is executed to clear the IRQaF flag while it is set to 1, then the
IRQbF flag is cleared by the execution of interrupt exception handling.
(2) When the IRQaF flag is cleared, there is contention with IRQb generation (IRQaF flag setting).
(IRQbF was 0 when ISR was read to clear the IRQaF flag, but IRQbF is set to 1 before ISR is
written to.)
If the above setting conditions (1) to (3) and generation conditions (1) and (2) are all fulfilled,
when the ISR write in generation condition (2) is performed the IRQbF flag will be cleared
inadvertently, and interrupt exception handling will not be executed.
However, this inadvertent clearing of the IRQbF flag will not occur if 0 is written to this flag even
once between generation conditions (1) and (2).
IRQaF
IRQbF
1 read 0 written
1 read 0 written
1 read 1 IRQb
written executed
1 read 0
written
Generation condition (1)
(Inadvertent clearing)
Generation condition (2)
Figure 5.9 IRQnF Flag when Interrupt Exception Handling is not Executed
Rev.3.00 Mar. 26, 2007 Page 109 of 682
REJ09B0353-0300