HD64F3039F18 Datasheet, PDF (207/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 7 I/O Ports
Port B Data Direction Register (PBDDR)
PBDDR is an 8-bit write-only register that can select input or output for each pin in port B.
Bit
7
6
5
4
3
2
1
0
PB₇ DDR — PB₅ DDR PB₄ DDR PB₃ DDR PB₂ DDR PB₁ DDR PB₀ DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Reserved bit
Port B data 7, 5 to 0
These bits select input or output for port B pins
A pin in port B becomes an output pin if the corresponding PBDDR bit is set to 1, and an input pin
if this bit is cleared to 0.
Bit 6 is reserved.
PBDDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PBDDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting. If a PBDDR bit is set to 1, the corresponding pin maintains its output
state in software standby mode.
Port B Data Register (PBDR)
PBDR is an 8-bit readable/writable register that stores data for pins PB₇, PB₅ to PB₀.
Bit
Initial value
Read/Write
7
PB ₇
0
R/W
6
—
0
R/W
5
PB ₅
0
R/W
4
PB ₄
0
R/W
3
PB ₃
0
R/W
2
PB ₂
0
R/W
1
PB ₁
0
R/W
0
PB ₀
0
R/W
Reserved bit
Port B data 7, 5 to 0
These bits store data for port B pins
When a bit in PBDDR is set to 1, if port B is read the value of the corresponding PBDR bit is
returned directly. When a bit in PBDDR is cleared to 0, if port B is read the corresponding pin
level is read. Bit 6 is reserved. Bit 6 can be written and read, but cannot be used for a port input or
output.
Rev.3.00 Mar. 26, 2007 Page 183 of 682
REJ09B0353-0300