HD64F3039F18 Datasheet, PDF (124/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 5 Interrupt Controller
5.4 Interrupt Operation
5.4.1 Interrupt Handling Process
The H8/3039 Group handles interrupts differently depending on the setting of the UE bit. When
UE = 1, interrupts are controlled by the I bit. When UE = 0, interrupts are controlled by the I and
UI bits. Table 5.4 indicates how interrupts are handled for all setting combinations of the UE, I,
and UI bits.
NMI interrupts are always accepted except in the reset and hardware standby states. IRQ interrupts
and interrupts from the on-chip supporting modules have their own enable bits. Interrupt requests
are ignored when the enable bits are cleared to 0.
Table 5.4 UE, I, and UI Bit Settings and Interrupt Handling
SYSCR
UE
1
0
CCR
I
UI
0
—
1
—
0
—
1
0
1
Description
All interrupts are accepted. Interrupts with priority level 1 have
higher priority.
No interrupts are accepted except NMI.
All interrupts are accepted. Interrupts with priority level 1 have
higher priority.
NMI and interrupts with priority level 1 are accepted.
No interrupts are accepted except NMI.
UE = 1
Interrupts IRQ₀, IRQ₁, IRQ₄, and IRQ₅ and interrupts from the on-chip supporting modules can all
be masked by the I bit in the CPU's CCR. Interrupts are masked when the I bit is set to 1, and
unmasked when the I bit is cleared to 0. Interrupts with priority level 1 have higher priority. Figure
5.4 is a flowchart showing how interrupts are accepted when UE = 1.
Rev.3.00 Mar. 26, 2007 Page 100 of 682
REJ09B0353-0300