HD64F3039F18 Datasheet, PDF (320/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 9 Programmable Timing Pattern Controller
9.2.3 Port B Data Direction Register (PBDDR)
PBDDR is an 8-bit write-only register that selects input or output for each pin in port B.
Bit
7
6
5
4
3
2
1
0
PB₇ DDR — PB₅ DDR PB₄ DDR PB₃ DDR PB₂ DDR PB₁ DDR PB₀ DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Reserved bit
Port B data direction 7, 5 to 0
These bits select input or
output for port B pins
Port B is multiplexed with pins TP₁₅, TP₁₃ to TP₈. Bits corresponding to pins used for TPC output
must be set to 1. For further information about PBDDR, see section 7.11, Port B.
9.2.4 Port B Data Register (PBDR)
PBDR is an 8-bit readable/writable register that stores TPC output data for groups 2 and 3, when
these TPC output groups are used.
Bit
Initial value
Read/Write
7
PB ₇
0
R/(W)^*
6
—
0
R/(W)*
5
PB ₅
0
R/(W)*
4
PB ₄
0
R/(W)*
3
PB ₃
0
R/(W)*
2
PB ₂
0
R/(W)*
1
PB ₁
0
R/(W)*
0
PB ₀
0
R/(W)^*
Reserved bit
Port B data 7, 5 to 0
These bits store output data
for TPC output groups 2 and 3
Note: * Bits selected for TPC output by NDERB settings become read-only bits.
For further information about PBDR, see section 7.11, Port B.
Rev.3.00 Mar. 26, 2007 Page 296 of 682
REJ09B0353-0300