HD64F3039F18 Datasheet, PDF (346/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 10 Watchdog Timer
Bit 2
CKS2
0
1
Bit 1
CKS1
0
1
0
1
Bit 0
CKS0
0
1
0
1
0
1
0
1
Description
φ/2
φ/32
φ/64
φ/128
φ/256
φ/512
φ/2048
φ/4096
(Initial value)
10.2.3 Reset Control/Status Register (RSTCSR)
RSTCSR is an 8-bit readable and writable* register that indicates when a reset signal has been
generated by watchdog timer overflow, and controls external output of the reset signal.
Note: * RSTCSR is write-protected by a password. For details see section 10.2.4, Notes on
Register Access.
Bit
7
6
5
4
3
2
1
0
WRST RSTOE —
—
—
—
—
—
Initial value
0
0
1
1
1
1
1
1
Read/Write R/(W)^*1 R/W
—
—
—
—
—
—
Reserved bits
Reset output enable^*2
Enables or disables external output of the reset signal
Watchdog timer reset
Indicates that a reset signal has been generated
Notes: 1. Only 0 can be written in bit 7 to clear the flag.
2. With the mask ROM version, enable and disable can be set. With the F-ZTAT version,
do not set enable.
Bits 7 and 6 are initialized by input of a reset signal at the RES pin. They are not initialized by
reset signals generated by watchdog timer overflow.
Rev.3.00 Mar. 26, 2007 Page 322 of 682
REJ09B0353-0300