HD64F3039F18 Datasheet, PDF (305/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 8 16-Bit Integrated Timer Unit (ITU)
Contention between General Register Read and Input Capture
If an input capture signal occurs during the T₃ state of a general register read cycle, the value
before input capture is read. See figure 8.66.
General register read cycle
T₁
T₂
T₃
φ
Address
GR address
Internal read signal
Input capture signal
GR
X
M
Internal data bus
X
Figure 8.66 Contention between General Register Read and Input Capture
Rev.3.00 Mar. 26, 2007 Page 281 of 682
REJ09B0353-0300