HD64F3039F18 Datasheet, PDF (304/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 8 16-Bit Integrated Timer Unit (ITU)
Contention between TCNT Write and Overflow or Underflow
If an overflow occurs in the T₃ state of a TCNT write cycle, writing takes priority and the counter
is not incremented. OVF is set to 1. The same holds for underflow. See figure 8.65.
TCNT write cycle
T₁
T₂
T₃
φ
Address
TCNT address
Internal write signal
TCNT input clock
Overflow signal
TCNT
OVF
H'FFFF
M
TCNT write data
Figure 8.65 Contention between TCNT Write and Overflow
Rev.3.00 Mar. 26, 2007 Page 280 of 682
REJ09B0353-0300