HD64F3039F18 Datasheet, PDF (249/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 8 16-Bit Integrated Timer Unit (ITU)
8.2.12 Timer Status Register (TSR)
TSR is an 8-bit register. The ITU has five TSRs, one in each channel.
Channel
0
1
2
3
4
Abbreviation
TSR0
TSR1
TSR2
TSR3
TSR4
Function
Indicates input capture, compare match, and overflow status
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
OVF IMFB IMFA
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
— R/(W)* R/(W)* R/(W)*
Reserved bits
Overflow flag
Status flag indicating
overflow or underflow
Input capture/compare match flag B
Status flag indicating GRB compare
match or input capture
Input capture/compare match flag A
Status flag indicating GRA compare
match or input capture
Note: * Only 0 can be written to clear the flag.
Each TSR is an 8-bit readable/writable register containing flags that indicate TCNT overflow or
underflow and GRA or GRB compare match or input capture. These flags are interrupt sources
and generate CPU interrupts if enabled by corresponding bits in the timer interrupt enable register
(TIER).
TSR is initialized to H'F8 by a reset and in standby mode.
Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 1.
Rev.3.00 Mar. 26, 2007 Page 225 of 682
REJ09B0353-0300