HD64F3039F18 Datasheet, PDF (534/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 17 Power-Down State
Bit 7—Software Standby (SSBY): Enables transition to software standby mode. When software
standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal
operation. To clear this bit, write 0.
Bit 7
SSBY
0
1
Description
SLEEP instruction causes transition to sleep mode
SLEEP instruction causes transition to software standby mode
(Initial value)
Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU
and on-chip supporting modules wait for the clock to settle when software standby mode is exited
by an external interrupt. If the clock is generated by a crystal resonator, set these bits according to
the clock frequency so that the waiting time (for the clock to stabilize) will be at least 7 ms. See
table 17.3. If an external clock is used, any setting is permitted.
Bit 6
STS2
0
1
Bit 5
STS1
0
1
0
0
1
Bit 4
STS0
0
1
0
1
0
1
—
Description
Waiting time = 8192 states
Waiting time = 16384 states
Waiting time = 32768 states
Waiting time = 65536 states
Waiting time = 131072 states
Waiting time = 1024 states
Illegal setting
(Initial value)
Rev.3.00 Mar. 26, 2007 Page 510 of 682
REJ09B0353-0300