HD64F3039F18 Datasheet, PDF (473/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 15 ROM
15.3.3 RAM Control Register (RAMCR)
RAMCR selects the RAM area used when emulating real-time reprogramming of the flash
memory.
Bit
7
6
5
4
3
2
1
0
—
—
—
— RAMS RAM2 RAM1 —
Modes ^{Initial value 1}
1
1
1
0
0
0
1
1 to 4 Read/Write —
—
—
—
R
R
R
—
Modes ^{Initial value 1}
1
1
1
0
0
0
1
5 to 7 Read/Write —
—
—
—
R/W* R/W* R/W* —
Note: * Cannot be set to 1 in mode 6.
Reserved bits
Reserved bit
RAM2/1
This bit is used with
bit 3 to set the RAM
area.
RAM select
This bit is used with
bits 2 and 1 to set
the RAM area.
Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 1.
Bit 3—RAM Select (RAMS): Is used with bits 2 to 1 to reassign an area to RAM (see table 15.5).
The initial setting for this bit is 0 in modes 5, 6, and 7 (internal flash memory enabled) and
programming is enabled.* In modes other than 5 to 7, 0 is always read and writing is disabled.
It is initialized by a reset and in hardware standby mode. It is not initialized in software standby
mode.
When bit 3 is set, all flash-memory blocks are protected from programming and erasing.
Bits 2 to 1—RAM2 to RAM1: These bits are used with bit 3 to reassign an area to RAM (see
table 15.5). The initial setting for this bit is 0 in modes 5, 6, and 7 (internal flash memory enabled)
and programming is enabled.* In modes other than 5 to 7, 0 is always read and writing is disabled.
They are initialized by a reset and in hardware standby mode. They are not initialized in software
standby mode.
Rev.3.00 Mar. 26, 2007 Page 449 of 682
REJ09B0353-0300