HD64F3039F18 Datasheet, PDF (290/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 8 16-Bit Integrated Timer Unit (ITU)
Figure 8.51 shows an example in which GRA is set to function as an input capture register
buffered by BRA, and TCNT is cleared by input capture B. The falling edge is selected as the
input capture edge at TIOCB. Both edges are selected as input capture edges at TIOCA. Because
of the buffer setting, when the TCNT value is captured into GRA at input capture A, the previous
GRA value is simultaneously transferred to BRA. Figure 8.52 shows the transfer timing.
TCNT value
H'0180
H'0160
Counter cleared by
input capture B
H'0005
H'0000
TIOCB
TIOCA
GRA
BRA
GRB
H'0005
Time
H'0160
H'0005
H'0160
H'0180
Input capture A
Figure 8.51 Register Buffering (Example 2: Buffering of Input Capture Register)
Rev.3.00 Mar. 26, 2007 Page 266 of 682
REJ09B0353-0300