HD64F3039F18 Datasheet, PDF (344/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 10 Watchdog Timer
10.2.2 Timer Control/Status Register (TCSR)
TCSR is an 8-bit readable and writable* register. Its functions include selecting the timer mode
and clock source.
Note: * TCSR is write-protected by a password. For details see section 10.2.4, Notes on
Register Access.
Bit
7
6
5
4
OVF WT/IT TME
—
Initial value
0
0
0
1
Read/Write R/(W)^* R/W R/W
—
3
2
1
0
—
CKS2 CKS1 CKS0
1
0
0
0
—
R/W
R/W
R/W
Reserved bits
Clock select
These bits select the
TCNT clock source
Timer enable
Selects whether TCNT runs or halts
Timer mode select
Selects the mode
Overflow flag
Status flag indicating overflow
Note: * Only 0 can be written to clear the flag.
Bits 7 to 5 are initialized to 0 by a reset and in standby mode. Bits 2 to 0 are initialized to 0 by a
reset. In software standby mode bits 2 to 0 are not initialized, but retain their previous values.
Rev.3.00 Mar. 26, 2007 Page 320 of 682
REJ09B0353-0300