HD64F3039F18 Datasheet, PDF (588/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Appendix A Instruction Set
Addressing Mode and
Instruction Length (bytes)
No. of
States^*1
Mnemonic
MOV.W @aa:24, Rd
MOV.W Rs, @ERd
MOV.W Rs, @(d:16,
ERd)
MOV.W Rs, @(d:24,
ERd)
MOV.W Rs, @–ERd
MOV.W Rs, @aa:16
MOV.W Rs, @aa:24
MOV.L #xx:32, Rd
MOV.L ERs, ERd
MOV.L @ERs, ERd
MOV.L @(d:16, ERs),
ERd
MOV.L @(d:24, ERs),
ERd
MOV.L @ERs+, ERd
MOV.L @aa:16, ERd
MOV.L @aa:24, ERd
MOV.L ERs, @ERd
MOV.L ERs, @(d:16,
ERd)
MOV.L ERs, @(d:24,
ERd)
MOV.L ERs, @–ERd
MOV.L ERs, @aa:16
MOV.L ERs, @aa:24
POP.W Rn
POP.L ERn
Operation
W @aa:24 → Rd16
W Rs16 → @ERd
W Rs16 → @(d:16, ERd)
W Rs16 → @(d:24, ERd)
W ERd32–2 → ERd32
Rs16 → @ERd
W Rs16 → @aa:16
W Rs16 → @aa:24
L #xx:32 → Rd32
L ERs32 → ERd32
L @ERs → ERd32
L @(d:16, ERs) → ERd32
L @(d:24, ERs) → ERd32
L @ERs → ERd32
ERs32+4 → ERs32
L @aa:16 → ERd32
L @aa:24 → ERd32
L ERs32 → @ERd
L ERs32 → @(d:16, ERd)
L ERs32 → @(d:24, ERd)
L ERd32–4 → ERd32
ERs32 → @ERd
L ERs32 → @aa:16
L ERs32 → @aa:24
W @SP → Rn16
SP+2 → SP
L @SP → ERn32
SP+4 → SP
6
2
4
8
2
4
6
6
2
4
6
10
4
6
8
4
6
10
4
6
8
Condition Code
I HNZVC
——
0—
8
——
0—
4
——
0—
6
——
0—
8
——
0—
6
——
——
——
——
——
——
0—
6
0—
8
0—
6
0—
2
0—
8
0—
10
——
0—
14
——
0—
10
——
——
——
——
0—
10
0—
12
0—
8
0—
10
——
0—
14
——
0—
10
——
——
2 ——
0—
10
0—
12
0—
6
4 ——
0—
10
Rev.3.00 Mar. 26, 2007 Page 564 of 682
REJ09B0353-0300