HD64F3039F18 Datasheet, PDF (219/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 8 16-Bit Integrated Timer Unit (ITU)
Block Diagram of Channels 0 and 1
ITU channels 0 and 1 are functionally identical. Both have the structure shown in figure 8.2.
TCLKA to TCLKD
φ, φ/2, φ/4, φ/8
Clock selector
Comparator
Control logic
TIOCA₀
TIOCB₀
IMIA0
IMIB0
OVI0
Module data bus
Legend:
TCNT:
Timer counter (16 bits)
GRA, GRB: General registers A and B (input capture/output compare registers) (16 bits × 2)
TCR:
Timer control register (8 bits)
TIOR:
Timer I/O control register (8 bits)
TIER:
Timer interrupt enable register (8 bits)
TSR:
Timer status register (8 bits)
Figure 8.2 Block Diagram of Channels 0 and 1 (for Channel 0)
Rev.3.00 Mar. 26, 2007 Page 195 of 682
REJ09B0353-0300