HD64F3039F18 Datasheet, PDF (251/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 8 16-Bit Integrated Timer Unit (ITU)
8.2.13 Timer Interrupt Enable Register (TIER)
TIER is an 8-bit register. The ITU has five TIERs, one in each channel.
Channel
0
1
2
3
4
Abbreviation
TIER0
TIER1
TIER2
TIER3
TIER4
Function
Enables or disables interrupt requests.
Bit
7
—
Initial value
1
Read/Write
—
6
5
—
—
1
1
—
—
4
3
2
1
0
—
—
OVIE IMIEB IMIEA
1
1
0
0
0
—
—
R/W R/W R/W
Reserved bits
Overflow interrupt enable
Enables or disables OVF
interrupts
Input capture/compare match
interrupt enable B
Enables or disables IMFB interrupts
Input capture/compare match
interrupt enable A
Enables or disables IMFA
interrupts
Each TIER is an 8-bit readable/writable register that enables and disables overflow interrupt
requests and general register compare match and input capture interrupt requests.
TIER is initialized to H'F8 by a reset and in standby mode.
Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 1.
Rev.3.00 Mar. 26, 2007 Page 227 of 682
REJ09B0353-0300