HD64F3039F18 Datasheet, PDF (299/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 8 16-Bit Integrated Timer Unit (ITU)
8.5.3 Interrupt Sources
Each ITU channel can generate a compare match/input capture A interrupt, a compare match/input
capture B interrupt, and an overflow interrupt. In total there are 15 interrupt sources, all
independently vectored. An interrupt is requested when the interrupt request flag and interrupt
enable bit are both set to 1.
The priority order of the channels can be modified in interrupt priority registers A and B (IPRA
and IPRB). For details see section 5, Interrupt Controller.
Table 8.10 lists the interrupt sources.
Table 8.10 ITU Interrupt Sources
Channel Interrupt Source
Description
Priority*
0
IMIA0
Compare match/input capture A0
High
IMIB0
Compare match/input capture B0
OVI0
Overflow 0
1
IMIA1
Compare match/input capture A1
IMIB1
Compare match/input capture B1
OVI1
Overflow 1
2
IMIA2
Compare match/input capture A2
IMIB2
Compare match/input capture B2
OVI2
Overflow 2
3
IMIA3
Compare match/input capture A3
IMIB3
Compare match/input capture B3
OVI3
Overflow 3
4
IMIA4
Compare match/input capture A4
IMIB4
Compare match/input capture B4
OVI4
Overflow 4
Low
Note: * The priority immediately after a reset is indicated. Inter-channel priorities can be
changed by settings in IPRA and IPRB.
Rev.3.00 Mar. 26, 2007 Page 275 of 682
REJ09B0353-0300