HD64F3039F18 Datasheet, PDF (481/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Automatic SCI Bit Rate Adjustment
Section 15 ROM
Start
bit
D0
D1
D2
D3
D4
D5
D6
D7
Stop
bit
Low period (9 bits) measured (H'00 data)
High period
(1 or more bits)
Figure 15.7 Measuring the Low Period of the Communication Data from the Host
When boot mode is initiated, this LSI measures the low period of the asynchronous SCI
communication data (H'00) transmitted continuously from the host (figure 15.7). The SCI
transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. This LSI
calculates the bit rate of the transmission from the host from the measured low period, and
transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should
confirm that this adjustment end indication (H'00) has been received normally, and transmit one
H'55 byte to the LSI. If reception cannot be performed normally, initiate boot mode again (reset),
and repeat the above operations. Depending on the host's transmission bit rate and the system
clock frequency of this LSI, there will be a discrepancy between the bit rates of the host and the
LSI. To ensure correct SCI operation, the host's transfer bit rate should be set to 4800 and 9600
bps*¹.
Table 15.7 shows typical host transfer bit rates and system clock frequencies for which automatic
adjustment of this LSI bit rate is possible. The boot program should be executed within this system
clock range*².
Table 15.7 System Clock Frequencies for which Automatic Adjustment of This LSI Bit
Rate Is Possible
Host Bit Rate (bps)
9600
4800
System Clock Frequency for which Automatic Adjustment
of This LSI Bit Rate Is Possible (MHz)
8 to 18
4 to 18
Notes: 1. The host bit rate settings are 4800 and 9600bps only. Do not use any other setting.
2. This LSI may automatically adjusts the bit rate except for bit rate and system clock
combinations as shown in table 15.7. However, the bit rate of the host and this LSI will
be different and subsequent transfers will not be carried out normally. Therefore,
always execute the boot mode within the range of the bit rate and system clock
combinations shown in table 15.7.
Rev.3.00 Mar. 26, 2007 Page 457 of 682
REJ09B0353-0300