HD64F3039F18 Datasheet, PDF (250/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 8 16-Bit Integrated Timer Unit (ITU)
Bit 2—Overflow Flag (OVF): This status flag indicates TCNT overflow or underflow.
Bit 2
OVF
Description
0
[Clearing condition]
(Initial value)
Read OVF when OVF = 1, then write 0 in OVF
1
[Setting condition]
TCNT overflowed from H'FFFF to H'0000, or underflowed from H'0000 to H'FFFF*
Notes: *
TCNT underflow occurs when TCNT operates as an up/down-counter. Underflow
occurs only under the following conditions:
1. Channel 2 operates in phase counting mode (MDF = 1 in TMDR)
2. Channels 3 and 4 operate in complementary PWM mode (CMD1 = 1 and CMD0 = 0
in TFCR)
Bit 1—Input Capture/Compare Match Flag B (IMFB): This status flag indicates GRB
compare match or input capture events.
Bit 1
IMFB
0
1
Description
[Clearing condition]
Read IMFB when IMFB = 1, then write 0 in IMFB
(Initial value)
[Setting conditions]
• TCNT = GRB when GRB functions as a compare match register.
• TCNT value is transferred to GRB by an input capture signal, when GRB functions
as an input capture register.
Bit 0—Input Capture/Compare Match Flag A (IMFA): This status flag indicates GRA
compare match or input capture events.
Bit 0
IMFA
0
1
Description
[Clearing condition]
Read IMFA when IMFA = 1, then write 0 in IMFA.
(Initial value)
[Setting conditions]
• TCNT = GRA when GRA functions as a compare match register.
• TCNT value is transferred to GRA by an input capture signal, when GRA functions
as an input capture register.
Rev.3.00 Mar. 26, 2007 Page 226 of 682
REJ09B0353-0300