HD64F3039F18 Datasheet, PDF (108/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 5 Interrupt Controller
5.1.2 Block Diagram
Figure 5.1 shows a block diagram of the interrupt controller.
NMI
input
IRQ input
OVF
TME
.......
...
ADI
ADIE
ISCR IER
IRQ input
section ISR
IPRA, IPRB
Interrupt
Priority
request
decision logic
Vector
number
Interrupt controller
Legend:
I:
Interrupt mask bit
IER: IRQ enable register
IPRA: Interrupt priority register A
IPRB: Interrupt priority register B
ISCR: IRQ sense control register
ISR: IRQ status register
SYSCR: System control register
UE:
User bit enable
UI:
User bit/interrupt mask bit
UE
SYSCR
Figure 5.1 Interrupt Controller Block Diagram
CPU
I
CCR
UI
Rev.3.00 Mar. 26, 2007 Page 84 of 682
REJ09B0353-0300