HD64F3039F18 Datasheet, PDF (592/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Appendix A Instruction Set
Addressing Mode and
Instruction Length (bytes)
No. of
States^*1
Mnemonic
DIVXU. W Rs, ERd
DIVXS. B Rs, Rd
DIVXS. W Rs, ERd
CMP.B #xx:8, Rd
CMP.B Rs, Rd
CMP.W #xx:16, Rd
CMP.W Rs, Rd
CMP.L #xx:32, ERd
CMP.L ERs, ERd
NEG.B Rd
NEG.W Rd
NEG.L ERd
EXTU.W Rd
EXTU.L ERd
EXTS.W Rd
EXTS.L ERd
Operation
W ERd32 ÷ Rs16 →ERd32
2
(Ed: remainder,
Rd: quotient)
(unsigned division)
B Rd16 ÷ Rs8 → Rd16
4
(RdH: remainder,
RdL: quotient)
(signed division)
W ERd32 ÷ Rs16 → ERd32
4
(Ed: remainder,
Rd: quotient)
(signed division)
B Rd8–#xx:8
2
B Rd8–Rs8
2
W Rd16–#xx:16
4
W Rd16–Rs16
2
L ERd32–#xx:32
6
L ERd32–ERs32
2
B 0–Rd8 → Rd8
2
W 0–Rd16 → Rd16
2
L 0–ERd32 → ERd32
2
W 0 → (<bits 15 to 8>
2
of Rd16)
L 0 → (<bits 31 to 16>
2
of Rd32)
W (<bit 7> of Rd16) →
2
(<bits 15 to 8> of Rd16)
L (<bit 15> of Rd32) →
2
(<bits 31 to 16> of
ERd32)
Condition Code
I HNZVC
— — (6) (7) — —
22
— — (8) (7) — —
16
— — (8) (7) — —
24
—
2
—
2
— (1)
4
— (1)
2
— (2)
4
— (2)
2
—
2
—
2
—
2
—— 0
0—
2
—— 0
0—
2
——
0—
2
——
0—
2
Rev.3.00 Mar. 26, 2007 Page 568 of 682
REJ09B0353-0300