HD64F3039F18 Datasheet, PDF (17/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

7.11.2 Register Descriptions ........................................................................................... 182
7.11.3 Pin Functions ....................................................................................................... 184
Section 8 16-Bit Integrated Timer Unit (ITU) ............................................................ 191
8.1 Overview........................................................................................................................... 191
8.1.1 Features................................................................................................................ 191
8.1.2 Block Diagrams ................................................................................................... 194
8.1.3 Input/Output Pins ................................................................................................. 199
8.1.4 Register Configuration......................................................................................... 201
8.2 Register Descriptions ........................................................................................................ 204
8.2.1 Timer Start Register (TSTR)................................................................................ 204
8.2.2 Timer Synchro Register (TSNC) ......................................................................... 206
8.2.3 Timer Mode Register (TMDR) ............................................................................ 208
8.2.4 Timer Function Control Register (TFCR)............................................................ 211
8.2.5 Timer Output Master Enable Register (TOER) ................................................... 214
8.2.6 Timer Output Control Register (TOCR) .............................................................. 216
8.2.7 Timer Counters (TCNT) ...................................................................................... 218
8.2.8 General Registers (GRA, GRB) ........................................................................... 219
8.2.9 Buffer Registers (BRA, BRB).............................................................................. 220
8.2.10 Timer Control Registers (TCR) ........................................................................... 221
8.2.11 Timer I/O Control Register (TIOR) ..................................................................... 223
8.2.12 Timer Status Register (TSR)................................................................................ 225
8.2.13 Timer Interrupt Enable Register (TIER) .............................................................. 227
8.3 CPU Interface.................................................................................................................... 228
8.3.1 16-Bit Accessible Registers ................................................................................. 228
8.3.2 8-Bit Accessible Registers ................................................................................... 231
8.4 Operation........................................................................................................................... 232
8.4.1 Overview.............................................................................................................. 232
8.4.2 Basic Functions.................................................................................................... 234
8.4.3 Synchronization ................................................................................................... 243
8.4.4 PWM Mode.......................................................................................................... 245
8.4.5 Reset-Synchronized PWM Mode......................................................................... 249
8.4.6 Complementary PWM Mode ............................................................................... 252
8.4.7 Phase Counting Mode .......................................................................................... 261
8.4.8 Buffering.............................................................................................................. 263
8.4.9 ITU Output Timing .............................................................................................. 269
8.5 Interrupts ........................................................................................................................... 272
8.5.1 Setting of Status Flags.......................................................................................... 272
8.5.2 Clearing of Status Flags ....................................................................................... 274
8.5.3 Interrupt Sources.................................................................................................. 275
8.6 Usage Notes ...................................................................................................................... 276
Rev.3.00 Mar. 26, 2007 Page xv of xxii
REJ09B0353-0300