HD64F3039F18 Datasheet, PDF (460/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 14 RAM
14.1.1 Block Diagram
Figure 14.1 shows a block diagram of the on-chip RAM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
Bus interface
SYSCR
H'FEF10*
H'FEF12*
H'FEF11*
H'FEF13*
On-chip RAM
H'FFF0E*
H'FFF0F*
Even addresses
Legend:
SYSCR: System control register
Note: * Lower 20 bits of the address
Odd addresses
Figure 14.1 RAM Block Diagram (H8/3039 in Modes 1, 5 and 7)
14.1.2 Register Configuration
The on-chip RAM is controlled by the system control register (SYSCR). Table 14.2 gives the
address and initial value of SYSCR.
Table 14.2 RAM Control Register
Address* Name
Abbreviation
R/W
H'FFF2
System control register
SYSCR
R/W
Note: * Lower 16 bits of the address
Initial Value
H'0B
Rev.3.00 Mar. 26, 2007 Page 436 of 682
REJ09B0353-0300