HD64F3039F18 Datasheet, PDF (221/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 8 16-Bit Integrated Timer Unit (ITU)
Block Diagrams of Channels 3 and 4
Figure 8.4 is a block diagram of channel 3. Figure 8.5 is a block diagram of channel 4.
TCLKA to
TCLKD
φ, φ/2,
φ/4, φ/8
Clock selector
Comparator
Control logic
TIOCA₃
TIOCB₃
IMIA3
IMIB3
OVI3
Module data bus
Legend:
TCNT3:
Timer counter 3 (16 bits)
GRA3, GRB3: General registers A3 and B3 (input capture/output compare registers)
(16 bits × 2)
BRA3, BRB3: Buffer registers A3 and B3 (input capture/output compare buffer registers)
(16 bits × 2)
TCR3:
Timer control register 3 (8 bits)
TIOR3:
Timer I/O control register 3 (8 bits)
TIER3:
Timer interrupt enable register 3 (8 bits)
TSR3:
Timer status register 3 (8 bits)
Figure 8.4 Block Diagram of Channel 3
Rev.3.00 Mar. 26, 2007 Page 197 of 682
REJ09B0353-0300