HD64F3039F18 Datasheet, PDF (266/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 8 16-Bit Integrated Timer Unit (ITU)
Input capture signal timing: Input capture on the rising edge, falling edge, or both edges can be
selected by settings in TIOR. Figure 8.25 shows the timing when the rising edge is selected. The
pulse width of the input capture signal must be at least 1.5 system clocks for single-edge capture,
and 2.5 system clocks for capture of both edges.
φ
Input-capture input
Internal input
capture signal
TCNT
N
GRA, GRB
N
Figure 8.25 Input Capture Signal Timing
Rev.3.00 Mar. 26, 2007 Page 242 of 682
REJ09B0353-0300