HD64F3039F18 Datasheet, PDF (277/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 8 16-Bit Integrated Timer Unit (ITU)
Setup Procedure for Complementary PWM Mode
Figure 8.33 shows a sample procedure for setting up complementary PWM mode.
Complementary PWM mode
1. Clear bits STR3 and STR4 to 0 in
TSTR to halt the timer counters.
Complementary PWM mode must be
set up while TCNT3 and TCNT4 are
Stop counting
halted.
1
2. Set bits TPSC2 to TPSC0 in TCR to
select the same counter clock source
for channels 3 and 4. If an external
Select counter clock
2
clock source is selected, select the
external clock edge(s) with bits
CKEG1 and CKEG0 in TCR. Do not
Select complementary
PWM mode
3
select any counter clear source
with bits CCLR1 and CCLR0 in TCR.
3. Set bits CMD1 and CMD0 in TFCR
to select complementary PWM mode.
Set TCNTs
4
TIOCA₃, TIOCB₃, TIOCA₄, TIOCB₄,
TOCXA₄, and TOCXB₄ automatically
become PWM output pins.
Set general registers
4. Clear TCNT4 to H'0000. Set the
5
non-overlap margin in TCNT3. Do not
set TCNT3 and TCNT4 to the same
value.
Start counters
6 ^{5. GRA3 is the waveform period}
register. Set the upper limit value of
TCNT3 minus 1 in GRA3. Set
transition times of the PWM output
Complementary PWM mode
waveforms in GRB3, GRA4, and
GRB4. Set times within the compare
match range of TCNT3 and TCNT4.
T ≤ X (X: initial setting of GRB3,
GRA4, or GRB4. T: initial setting of
TCNT3)
6. Set bits STR3 and STR4 in TSTR to
1 to start TCNT3 and TCNT4.
Note: After exiting complementary PWM mode, to resume operating in complementary
PWM mode, follow the entire setup procedure from step 1 again.
Figure 8.33 Setup Procedure for Complementary PWM Mode (Example)
Rev.3.00 Mar. 26, 2007 Page 253 of 682
REJ09B0353-0300