HD64F3039F18 Datasheet, PDF (613/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Appendix A Instruction Set
Instruction Mnemonic
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access Access Operation
I
J
K
L
M
N
STC
STC CCR, Rd
1
STC CCR, @ERd
2
1
STC CCR, @(d:16, ERd)
3
1
STC CCR, @(d:24, ERd)
5
1
STC CCR, @–ERd
2
1
2
STC CCR, @aa:16
3
1
STC CCR, @aa:24
4
1
SUB
SUB.B Rs, Rd
1
SUB.W #xx:16, Rd
2
SUB.W Rs, Rd
1
SUB.L #xx:32, ERd
3
SUB.L ERs, ERd
1
SUBS
SUBS #1/2/4, ERd
1
SUBX
SUBX #xx:8, Rd
1
SUBX Rs, Rd
1
TRAPA
TRAPA #x:2 Normal
2
1
2
4
Advanced
2
2
2
4
XOR
XOR.B #xx:8, Rd
1
XOR.B Rs, Rd
1
XOR.W #xx:16, Rd
2
XOR.W Rs, Rd
1
XOR.L #xx:32, ERd
3
XOR.L ERs, ERd
2
XORC
XORC #xx:8, CCR
1
Notes: 1. n is the value set in register R4L or R4. The source and destination are accessed n+1
times each.
2. Not used with this LSI.
Rev.3.00 Mar. 26, 2007 Page 589 of 682
REJ09B0353-0300