HD64F3039F18 Datasheet, PDF (527/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 16 Clock Pulse Generator
Table 16.4 and figure 16.7 show the timing for the external clock output stabilization delay time.
The oscillator and duty correction circuit have the function of regulating the waveform of the
external clock input to the EXTAL pin. When the specified clock signal is input to the EXTAL
pin, internal clock signal output is confirmed after the elapse of the external clock output
stabilization delay time (t_DEXT). As clock signal output is not confirmed during the t_DEXT period, the
reset signal should be driven low and the reset state maintained during this time.
Table 16.4 External Clock Output Stabilization Delay Time
Conditions: V_CC = 2.7 V to 5.5 V, AV_CC = 2.7 V to 5.5 V, V_SS = AV_SS = 0 V
Item
Symbol Min
External clock output stabilization
t_DEXT*
500
delay time
Note: * t_DEXT includes a 10 t_cyc RES pulse width (t_RESW).
Max
—
Unit
µs
Notes
Figure 16.7
V_CC 2.7 V
STBY
V_IH
EXTAL
φ
RES
t_DEXT*
Note: * t_DEXT includes a 10 t_cyc RES pulse width (t_RESW).
Figure 16.7 External Clock Output Stabilization Delay Time
Rev.3.00 Mar. 26, 2007 Page 503 of 682
REJ09B0353-0300