HD64F3039F18 Datasheet, PDF (347/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 10 Watchdog Timer
Bit 7—Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that
TCNT has overflowed and generated a reset signal. This reset signal resets the entire chip
internally. If bit RSTOE is set to 1, this reset signal is also output (low) at the RESO pin*¹ to
initialize external system devices.
Bit 7
WRST
0
1
Description
[Clearing conditions]
(Initial value)
(1) Cleared to 0 by reset signal input at RES pin
(2) Cleared by reading WRST when WRST = 1, then writing 0 in WERST
[Setting condition]
Set when TCNT overflow generates a reset signal during watchdog timer operation
Bit 6—Reset Output Enable (RSTOE): Enables or disables external output at the RESO pin*¹ of
the reset signal generated if TCNT overflows during watchdog timer operation.
Bit 6
RSTOE
Description
0
Reset signal is not output externally
1
Reset signal is output externally*²
Notes: 1. Mask ROM version. Dedicated FWE input pin for F-ZTAT version.
2. Mask ROM version. Do not set to 1 with the F-ZTAT version.
(Initial value)
Bits 5 to 0—Reserved: These bits cannot be modified and are always read as 1.
Rev.3.00 Mar. 26, 2007 Page 323 of 682
REJ09B0353-0300