HD64F3039F18 Datasheet, PDF (490/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 15 ROM
15.5.3 Erase Mode
Flash memory erasing should be performed block by block following the procedure shown in the
erase/erase-verify flowchart (single-block erase) shown in figure 15.12.
For the wait time (x, y, z, α, β, γ, ε, η) after setting or clearing of each bit in the flash memory
control register (FLMCR) and the maximum erase count (N), see table 18.15.
To erase the contents of flash memory, make a 1 bit setting for the flash memory area to be erased
in erase block register (EBR) at least (x) µs after setting the SWE bit to 1 in FLMCR. Next, the
watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. Set a value
greater than (z) ms + (y + α + ß) µs as the WDT overflow period. Preparation for entering erase
mode (erase setup) is performed next by setting the ESU bit in FLMCR. The operating mode is
then switched to erase mode by setting the E bit in FLMCR after the elapse of at least (y) µs.
The time during which the E bit is set is the flash memory erase time. Ensure that the erase time
does not exceed (z) ms.
Note: With flash memory erasing, preprogramming (setting all data in the memory to be erased
to "0") is not necessary before starting the erase procedure.
15.5.4 Erase-Verify Mode
In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
After the elapse of the fixed erase time, clear the E bit in FLMCR, then wait for at least (α) µs
before clearing the ESU bit to exit erase mode. After exiting erase mode, the watchdog timer
setting is also cleared. The operating mode is then switched to erase-verify mode by setting the EV
bit in FLMCR. Before reading in erase-verify mode, a dummy write of H'FF data should be made
to the addresses to be read. The dummy write should be executed after the elapse of (γ) µs or more.
When the flash memory is read in this state (verify data is read in 16-bit units), the data at the
latched address is read. Wait at least (ε) µs after the dummy write before performing this read
operation. If the read data has been erased (all "1"), a dummy write is performed to the next
address, and erase-verify is performed. If the read data is unerased, set erase mode again, and
repeat the erase/erase-verify sequence as before. However, do not repeat the erase/erase-verify
sequence more than (N) times.
Rev.3.00 Mar. 26, 2007 Page 466 of 682
REJ09B0353-0300