HD64F3039F18 Datasheet, PDF (130/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 5 Interrupt Controller
5.4.3 Interrupt Response Time
Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the
first instruction of the interrupt service routine is executed.
Table 5.5 Interrupt Response Time
External Memory
No. Item
On-Chip
Memory
8-Bit Bus
2 States
3 States
1
Interrupt priority decision
2
Maximum number of states
2*¹
1 to 23
2*¹
1 to 27
2*¹
1 to 31*⁴
until end of current instruction
3
Saving PC and CCR to stack
4
4
Vector fetch
4
5
Instruction prefetch*²
4
6
Internal processing*³
4
8
12*⁴
8
12*⁴
8
12*⁴
4
4
Total
19 to 41
31 to 57
43 to 73
Notes: 1. 1 state for internal interrupts.
2. Prefetch after the interrupt is accepted and prefetch of the first instruction in the interrupt
service routine.
3. Internal processing after the interrupt is accepted and internal processing after prefetch.
4. The number of states increases if wait states are inserted in external memory access.
Rev.3.00 Mar. 26, 2007 Page 106 of 682
REJ09B0353-0300