HD64F3039F18 Datasheet, PDF (465/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

15.2.2 Block Diagram
Figure 15.1 shows a block diagram of the flash memory.
Section 15 ROM
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
FLMCR^*2
EBR^*2
RAMCR^*2
FLMSR^*2
Bus interface/controller
Operating
mode
FWE pin^*1
Mode pins
H'00000
H'00002
H'00001
H'00003
On-chip Flash memory
(128 kbytes)
H'1FFFC H'1FFFD
H'1FFFE H'1FFFF
Legend:
even address odd address
FLMCR: Flash memory control register
EBR: Erase block register
RAMCR: RAM control register
FLMSR: Flash memory status register
Notes: 1. Functions as the FWE pin in the flash memory versions and as the RESO pin in the
mask ROM versions.
2. The registers that control the flash memory versions (FLMCR, EBR, RAMCR, and
FLMSR) are used in the flash memory versions only. They are not provided in the
mask ROM versions. Reading the corresponding addresses in a mask ROM version
will always return 1s, and writes to these addresses are disabled.
Figure 15.1 Block Diagram of Flash Memory
Rev.3.00 Mar. 26, 2007 Page 441 of 682
REJ09B0353-0300