HD64F3039F18 Datasheet, PDF (354/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 10 Watchdog Timer
10.5 Usage Notes
Contention between TCNT Write and Increment
If a timer counter clock pulse is generated during the T3 state of a write cycle to TCNT, the write
takes priority and the timer count is not incremented. See figure 10.8.
Write cycle: CPU writes to TCNT
T₁
T₂
T₃
φ
TCNT
Internal write
signal
TCNT input
clock
TCNT
N
M
Counter write data
Figure 10.8 Contention between TCNT Write and Increment
Changing CKS2 to CKS0 Values
Halt TCNT by clearing the TME bit to 0 in TCSR before changing the values of bits CKS2 to
CKS0.
Rev.3.00 Mar. 26, 2007 Page 330 of 682
REJ09B0353-0300