HD64F3039F18 Datasheet, PDF (76/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 2 CPU
including NMI, are disabled during the reset exception-handling sequence and immediately after it
ends.
Interrupt Exception Handling and Trap Instruction Exception Handling: When these
exception-handling sequences begin, the CPU references the stack pointer (ER7) and pushes the
program counter and condition code register on the stack. Next, if the UE bit in the system control
register (SYSCR) is set to 1, the CPU sets this set to 1, the CPU sets the I bit in the condition code
register to 1. If the UE bit is cleared to 0, the CPU sets both the I bit and the UI bit in the condition
code register to 1. Then the CPU fetches a start address from the exception vector table and
execution branches to that address.
Figure 2.14 shows the stack after the exception-handling sequence.
SPÐ4
SPÐ3
SPÐ2
SPÐ1
SP (ER7)
Stack area
SP (ER7)
SP+1
SP+2
SP+3
SP+4
CCR
PC
Even
address
Before exception
handling starts
Legend:
CCR: Condition code register
SP: Stack pointer
Pushed on stack
After exception
handling ends
Notes: 1. PC is the address of the first instruction executed after the return from the
exception-handling routine.
2. Registers must be saved and restored by word access or longword access,
starting at an even address.
Figure 2.14 Stack Structure after Exception Handling
Rev.3.00 Mar. 26, 2007 Page 52 of 682
REJ09B0353-0300