HD64F3039F18 Datasheet, PDF (117/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 5 Interrupt Controller
5.2.3 IRQ Status Register (ISR)
ISR is an 8-bit readable/writable register that indicates the status of IRQ₀, IRQ₁, IRQ₄, and IRQ₅
interrupt requests.
Bit
7
—
Initial value
0
Read/Write
—
6
5
4
3
— IRQ5F IRQ4F —
0
0
0
0
— R/(W)* R/(W)* —
2
1
0
— IRQ1F IRQ0F
0
0
0
— R/(W)* R/(W)*
Reserved bits
Reserved bits
IRQ₅ to IRQ₄ flags
These bits indicate IRQ₅ and IRQ₄
interrupt request status
IRQ₁, IRQ₀ flags
These bits indicates IRQ₁ and IRQ₀
interrupt request status
Note: * Only 0 can be written, to clear flags.
ISR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7, 6, 3 and 2—Reserved: These bits cannot be modified and are always read as 0.
Bits 5, 4, 1 and 0—IRQ₅, IRQ₄, IRQ₁ and IRQ₀ Flags (IRQ5F, IRQ4F, IRQ1F, and IRQ0F):
These bits indicate the status of IRQ₅, IRQ₄, IRQ₁, and IRQ₀ interrupt requests.
Bits 5, 4, 1, and 0
IRQ5F, IRQ4F,
IRQ1F, and IRQ0F
Description
0
[Clearing conditions]
(Initial value)
• 0 is written in IRQnF after reading the IRQnF flag when IRQnF = 1.
• IRQnSC = 0, IRQn input is high, and interrupt exception handling is
carried out.
• IRQnSC = 1 and IRQn interrupt exception handling is carried out.
1
[Setting conditions]
• IRQnSC = 0 and IRQn input is low.
• IRQnSC = 1 and IRQn input changes from high to low.
Note: n = 5, 4, 1 and 0
Rev.3.00 Mar. 26, 2007 Page 93 of 682
REJ09B0353-0300