HD64F3039F18 Datasheet, PDF (298/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 8 16-Bit Integrated Timer Unit (ITU)
φ
TCNT
Overflow
signal
OVF
H'FFFF
H'0000
OVI
Figure 8.59 Timing of Setting of OVF
8.5.2 Clearing of Status Flags
If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is
cleared. Figure 8.60 shows the timing.
TSR write cycle
T₁
T₂
T₃
φ
Address
TSR address
IMF, OVF
Figure 8.60 Timing of Clearing of Status Flags
Rev.3.00 Mar. 26, 2007 Page 274 of 682
REJ09B0353-0300