HD64F3039F18 Datasheet, PDF (107/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 5 Interrupt Controller
Section 5 Interrupt Controller
5.1 Overview
5.1.1 Features
The interrupt controller has the following features:
• Interrupt priority registers (IPRs) for setting interrupt priorities
Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis
in interrupt priority registers A and B (IPRA and IPRB).
• Three-level masking by the I and UI bits in the CPU condition code register (CCR)
• Independent vector addresses
All interrupts are independently vectored; the interrupt service routine does not have to
identify the interrupt source.
• Five external interrupt pins
NMI has the highest priority and is always accepted; either the rising or falling edge can be
selected. For each of IRQ₀, IRQ₁, IRQ₄, and IRQ₅, sensing of the falling edge or level sensing
can be selected independently.
Rev.3.00 Mar. 26, 2007 Page 83 of 682
REJ09B0353-0300