HD64F3039F18 Datasheet, PDF (700/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Appendix D Pin States
D.2 Pin States at Reset
Reset in T1 State
Figure D.1 is a timing diagram for the case in which RES goes low during the T1 state of an
external memory access cycle. As soon as RES goes low, all ports are initialized to the input state.
AS, RD, and WR go high, and the data bus goes to the high-impedance state. The address bus is
initialized to the low output level 0.5 state after the low level of RES is sampled. Sampling of RES
takes place at the fall of the system clock (φ).
Access to external address
T₁
T₂
T₃
φ
RES
Internal
reset signal
Address bus
(modes 1, 3, 5)
H'000000
AS (modes 1, 3, 5)
High
RD (read access)
(modes 1, 3, 5)
High
WR (write access)
(modes 1, 3, 5)
Data bus
(write access)
(modes 1, 3, 5)
High
I/O port
(modes 1, 3, 5 to 7)
High impedance
High impedance
Figure D.1 Reset during Memory Access (Reset during T1 State)
Rev.3.00 Mar. 26, 2007 Page 676 of 682
REJ09B0353-0300