HD64F3039F18 Datasheet, PDF (297/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 8 16-Bit Integrated Timer Unit (ITU)
Timing of Setting of IMFA and IMFB by Input Capture
IMFA and IMFB are set to 1 by an input capture signal. The TCNT contents are simultaneously
transferred to the corresponding general register. Figure 8.58 shows the timing.
φ
Input capture
signal
IMF
TCNT
N
GR
N
IMI
Figure 8.58 Timing of Setting of IMFA and IMFB by Input Capture
Timing of Setting of Overflow Flag (OVF)
OVF is set to 1 when TCNT overflows from H'FFFF to H'0000 or underflows from H'0000 to
H'FFFF. Figure 8.59 shows the timing.
Rev.3.00 Mar. 26, 2007 Page 273 of 682
REJ09B0353-0300