HD64F3039F18 Datasheet, PDF (343/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 10 Watchdog Timer
10.1.4 Register Configuration
Table 10.2 summarizes the WDT registers.
Table 10.2 WDT Registers
Address*¹
Write*² Read
Name
Abbreviation
H'FFA8 H'FFA8 Timer control/status register TCSR
H'FFA9 Timer counter
TCNT
H'FFAA H'FFAB Reset control/status register RSTCSR
Notes: 1. Lower 16 bits of the address.
2. Write word data starting at this address.
3. Only 0 can be written in bit 7 to clear the flag.
R/W
R/(W)*³
R/W
R/(W)*³
Initial Value
H'18
H'00
H'3F
10.2 Register Descriptions
10.2.1 Timer Counter (TCNT)
TCNT is an 8-bit readable and writable* up-counter.
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from an internal
clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from
H'FF to H'00), the OVF bit is set to 1 in TCSR. TCNT is initialized to H'00 by a reset and when
the TME bit is cleared to 0.
Note: * TCNT is write-protected by a password. For details see section 10.2.4, Notes on
Register Access.
Rev.3.00 Mar. 26, 2007 Page 319 of 682
REJ09B0353-0300