HD64F3039F18 Datasheet, PDF (232/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 8 16-Bit Integrated Timer Unit (ITU)
8.2.3 Timer Mode Register (TMDR)
TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 4. It also
selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2.
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
—
MDF FDIR PWM4 PWM3 PWM2 PWM1 PWM0
1
0
0
0
0
0
0
0
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PWM mode 4 to 0
These bits select PWM
Flag direction
mode for channels 4 to 0
Selects the setting condition for the overflow
flag (OVF) in timer status register 2 (TSR2)
Phase counting mode flag
Selects phase counting mode for channel 2
Reserved bit
TMDR is initialized to H'80 by a reset and in standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Bit 6—Phase Counting Mode Flag (MDF): Selects whether channel 2 operates normally or in
phase counting mode.
Bit 6
MDF
0
1
Description
Channel 2 operates normally
Channel 2 operates in phase counting mode
(Initial value)
When MDF is set to 1 to select phase counting mode, timer counter 2 (TCNT2) operates as an
up/down-counter and pins TCLKA and TCLKB become counter clock input pins. TCNT2 counts
both rising and falling edges of TCLKA and TCLKB, and counts up or down as follows.
Counting Direction
TCLKA pin
TCLKB pin
Down-Counting
High
Low
Low
High
High
Up-Counting
Low
Low
High
Rev.3.00 Mar. 26, 2007 Page 208 of 682
REJ09B0353-0300