HD64F3039F18 Datasheet, PDF (59/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 2 CPU
Table 2.5 Logic Operation Instructions
Instruction Size* Function
AND
B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR
B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR
B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
NOT
B/W/L ¬ Rd → Rd
Takes the one's complement of general register contents.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
Table 2.6 Shift Instructions
Instruction Size* Function
SHAL,
SHAR
B/W/L
Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
SHLL,
SHLR
B/W/L
Rd (shift) → Rd
Performs a logical shift on general register contents.
ROTL,
ROTR
B/W/L
Rd (rotate) → Rd
Rotates general register contents.
ROTXL,
ROTXR
B/W/L
Rd (rotate) → Rd
Rotates general register contents through the carry bit.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
Rev.3.00 Mar. 26, 2007 Page 35 of 682
REJ09B0353-0300