HD64F3039F18 Datasheet, PDF (263/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 8 16-Bit Integrated Timer Unit (ITU)
Output compare timing: The compare match signal is generated in the last state in which TCNT
and the general register match (when TCNT changes from the matching value to the next value).
When the compare match signal is generated, the output value selected in TIOR is output at the
output compare pin (TIOCA or TIOCB). When TCNT matches a general register, the compare
match signal is not generated until the next counter clock pulse.
Figure 8.22 shows the output compare timing.
φ
TCNT input
clock
TCNT
GR
Compare
match signal
TIOCA,
TIOCB
N
N+1
N
Figure 8.22 Output Compare Timing
Rev.3.00 Mar. 26, 2007 Page 239 of 682
REJ09B0353-0300