HD64F3039F18 Datasheet, PDF (18/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 9 Programmable Timing Pattern Controller ................................................. 291
9.1 Overview........................................................................................................................... 291
9.1.1 Features................................................................................................................ 291
9.1.2 Block Diagram..................................................................................................... 292
9.1.3 TPC Pins .............................................................................................................. 293
9.1.4 Registers............................................................................................................... 294
9.2 Register Descriptions ........................................................................................................ 295
9.2.1 Port A Data Direction Register (PADDR) ........................................................... 295
9.2.2 Port A Data Register (PADR).............................................................................. 295
9.2.3 Port B Data Direction Register (PBDDR) ........................................................... 296
9.2.4 Port B Data Register (PBDR) .............................................................................. 296
9.2.5 Next Data Register A (NDRA) ............................................................................ 297
9.2.6 Next Data Register B (NDRB)............................................................................. 299
9.2.7 Next Data Enable Register A (NDERA).............................................................. 301
9.2.8 Next Data Enable Register B (NDERB) .............................................................. 302
9.2.9 TPC Output Control Register (TPCR) ................................................................. 303
9.2.10 TPC Output Mode Register (TPMR) ................................................................... 306
9.3 Operation .......................................................................................................................... 308
9.3.1 Overview.............................................................................................................. 308
9.3.2 Output Timing ..................................................................................................... 309
9.3.3 Normal TPC Output............................................................................................. 310
9.3.4 Non-Overlapping TPC Output............................................................................. 312
9.3.5 TPC Output Triggering by Input Capture ............................................................ 314
9.4 Usage Notes ...................................................................................................................... 315
9.4.1 Operation of TPC Output Pins ............................................................................. 315
9.4.2 Note on Non-Overlapping Output........................................................................ 315
Section 10 Watchdog Timer............................................................................................. 317
10.1 Overview........................................................................................................................... 317
10.1.1 Features................................................................................................................ 317
10.1.2 Block Diagram..................................................................................................... 318
10.1.3 Pin Configuration................................................................................................. 318
10.1.4 Register Configuration......................................................................................... 319
10.2 Register Descriptions ........................................................................................................ 319
10.2.1 Timer Counter (TCNT)........................................................................................ 319
10.2.2 Timer Control/Status Register (TCSR)................................................................ 320
10.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 322
10.2.4 Notes on Register Access..................................................................................... 324
10.3 Operation .......................................................................................................................... 326
10.3.1 Watchdog Timer Operation ................................................................................. 326
10.3.2 Interval Timer Operation ..................................................................................... 327
Rev.3.00 Mar. 26, 2007 Page xvi of xxii
REJ09B0353-0300