HD64F3039F18 Datasheet, PDF (287/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 8 16-Bit Integrated Timer Unit (ITU)
8.4.8 Buffering
Buffering operates differently depending on whether a general register is an output compare
register or an input capture register, with further differences in reset-synchronized PWM mode and
complementary PWM mode. Buffering is available only in channels 3 and 4. Buffering operations
under the conditions mentioned above are described next.
• General register used for output compare
The buffer register value is transferred to the general register at compare match. See
figure 8.46.
Compare match signal
BR
GR
Comparator
TCNT
Figure 8.46 Compare Match Buffering
• General register used for input capture
The TCNT value is transferred to the general register at input capture. The previous general
register value is transferred to the buffer register.
See figure 8.47.
Input capture signal
BR
GR
TCNT
Figure 8.47 Input Capture Buffering
• Complementary PWM mode
The buffer register value is transferred to the general register when TCNT3 and TCNT4
change counting direction. This occurs at the following two times:
 When TCNT3 matches GRA3
 When TCNT4 underflows
• Reset-synchronized PWM mode
The buffer register value is transferred to the general register at compare match A3.
Rev.3.00 Mar. 26, 2007 Page 263 of 682
REJ09B0353-0300