HD64F3039F18 Datasheet, PDF (475/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 15 ROM
15.3.4 Flash Memory Status Register (FLMSR)
The flash memory status register (FLMSR) detects flash memory errors.
Bit
7
6
5
4
3
2
1
0
FLER —
—
—
—
—
—
—
Initial value
0
1
1
1
1
1
1
1
Read/Write R
—
—
—
—
—
—
—
Reserved bits
Flash memory error
Status flag indicating that
an error was detected during
programming or erasing
Bit 7—Flash Memory Error (FLER): Indicates that an error occurred while flash memory was
being programmed or erased. When bit 7 is set, flash memory is placed in an error-protect mode.
Bit 7
FLER
Description
0
Flash memory program/erase protection (error protection*¹) is disabled (Initial value)
[Clearing condition]
WDT reset, reset by RES pin, or hardware standby mode
1
An error has occurred during flash memory programming/erasing
Flash memory program/erase protection (error protection*¹) is enabled
[Setting conditions]
1. Flash memory was read*² while being programmed or erased (including vector or
instruction fetch, but not including reading of a RAM area overlapped onto flash
memory).
2. A hardware exception-handling sequence (other than a reset, invalid instruction,
trap instruction, or zero-divide exception) was executed just before programming or
erasing.*³
3. The SLEEP instruction (including software standby mode) was executed during
programming or erasing.
Notes: 1. For details, see section 15.6.3, Error Protection.
2. The read data has undetermined values.
3. Before stack and vector read by exception handling.
Bits 6 to 0—Reserved: These bits cannot be modified and are always read as 1.
Rev.3.00 Mar. 26, 2007 Page 451 of 682
REJ09B0353-0300