HD64F3039F18 Datasheet, PDF (412/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 11 Serial Communication Interface
Restrictions in Synchronous Mode
When data transmission is performed using an external clock source as the serial clock, an interval
of at least 5 states is necessary between clearing the TDRE flag in SSR and the start (falling edge)
of the first transmit clock pulse corresponding to each frame (figure 11.22). This interval is also
necessary when performing continuous transmission. If this condition is not satisfied, an operation
error may occur.
SCK
t*
t*
TDRE
TXD
X0 X1 X2 X3 X4 X5 X6 X7 Y0 Y1 Y2 Y3
Note: * Make sure that t is at least 5 states.
Continuous transmission
Figure 11.22 Transmission in Synchronous Mode (Example)
Rev.3.00 Mar. 26, 2007 Page 388 of 682
REJ09B0353-0300