HD64F3039F18 Datasheet, PDF (333/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 9 Programmable Timing Pattern Controller
Table 9.3 TPC Operating Conditions
NDER
0
1
DDR
0
1
0
1
Pin Function
Generic input port
Generic output port
Generic input port (but the DR bit is a read-only bit, and when compare
match occurs, the NDR bit value is transferred to the DR bit)
TPC pulse output
Sequential output of up to 16-bit patterns is possible by writing new output data to NDRA and
NDRB before the next compare match. For information on non-overlapping operation, see section
9.3.4, Non-Overlapping TPC Output.
9.3.2 Output Timing
If TPC output is enabled, NDRA/NDRB contents are transferred to PADR/PBDR and output
when the selected compare match event occurs. Figure 9.3 shows the timing of these operations
for the case of normal output in groups 0 and 1, triggered by compare match A.
φ
TCNT
GRA
Compare
match A signal
NDRA
N
N+1
N
n
PADR
m
n
TP₀ to TP₇
m
n
Figure 9.3 Timing of Transfer of Next Data Register Contents and Output (Example)
Rev.3.00 Mar. 26, 2007 Page 309 of 682
REJ09B0353-0300