HD64F3039F18 Datasheet, PDF (568/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 18 Electrical Characteristics
Condition A Condition B
Item
10 MHz
Symbol Min Max
18 MHz
Test
Min Max Unit Conditions
Write data delay time
Write data setup time 1
t_WDD
— 75
— 55 ns Figure 18.7,
t
WDS1
40 —
10 —
Figure 18.8
Write data setup time 2
t
WDS2
–10 —
–10 —
Write data hold time
t_WDH
20 —
20 —
Read data access time 1
t_ACC1*
— 100 — 50
Read data access time 2
t_ACC2*
— 200 — 105
Read data access time 3
t_ACC3*
— 50
— 20
Read data access time 4
t_ACC4*
— 150 — 80
Precharge time
t_PCH*
60 —
40 —
Wait setup time
t_WTS
40 —
25 — ns Figure 18.9
Wait hold time
t_WTH
10 —
5
—
Note: * For condition A, the following times depend on the clock cycle time as shown below.
t_ACC1 = 1.5 × t_cyc –50 (ns)
t_ACC2 = 2.5 × t_cyc –50 (ns)
t_ACC3 = 1.0 × t_cyc –50 (ns)
t_ACC4 = 2.0 × t_cyc –50 (ns)
t_WSW1 = 1.0 × t_cyc –40
t_WSW2 = 1.5 × t_cyc –40
t_PCH = 1.0 × t_cyc –40
(ns)
(ns)
(ns)
For condition B, the following times depend on the clock cycle time as shown below.
t_ACC1 = 1.5 × t_cyc –34 (ns)
t_ACC2 = 2.5 × t_cyc –34 (ns)
t_ACC3 = 1.0 × t_cyc –36 (ns)
t_ACC4 = 2.0 × t_cyc –31 (ns)
t_WSW1 = 1.0 × t_cyc –24
t_WSW2 = 1.5 × t_cyc –22
t_PCH = 1.0 × t_cyc –21
(ns)
(ns)
(ns)
Rev.3.00 Mar. 26, 2007 Page 544 of 682
REJ09B0353-0300