HD64F3039F18 Datasheet, PDF (197/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 7 I/O Ports
7.10.2 Register Descriptions
Table 7.15 summarizes the registers of port A.
Table 7.15 Port A Registers
Address* Name
Abbreviation R/W
H'FFD1
Port A data direction PADDR
W
register
H'FFD3
Port A data register PADR
R/W
Note: * Lower 16 bits of the address.
Initial Value
Modes 1, 5, and 7 Mode 3
H'00
H'80
H'00
H'00
Port A Data Direction Register (PADDR)
PADDR is an 8-bit write-only register that can select input or output for each pin in port A. The
corresponding PADDR bit should also be set when a pin is used as a TPC output.
Modes
1, 5, and 7
Mode 3
Bit
Initial value
Read/Write
Initial value
Read/Write
7
6
5
4
3
2
1
0
PA₇ DDR PA₆ DDR PA₅ DDR PA₄ DDR PA₃ DDR PA₂ DDR PA₁ DDR PA₀ DDR
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
1
0
0
0
0
0
0
0
—
W
W
W
W
W
W
W
Port A data direction 7 to 0
These bits select input or output for port A pins
A pin in port A becomes an output pin if the corresponding PADDR bit is set to 1, and an input
pin if this bit is cleared to 0. However, in mode 3, PA₇ DDR is fixed at 1, and PA7 functions as an
address output pin.
PADDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PADDR is initialized to H'00 in modes 1, 5 and 7 and to H'80 in mode 3 by a reset and in
hardware standby mode. In software standby mode it retains its previous setting. If a PADDR bit
is set to 1, the corresponding pin maintains its output state in software standby mode.
Rev.3.00 Mar. 26, 2007 Page 173 of 682
REJ09B0353-0300